General Laptop Power Supply diagram

(VALW section of ADP+,+3V,+5V) as a Voltage requirerment and Microcontroler system

General Laptop Power Supply diagram (VALW section of ADP+,+3V,+5V) as a Voltage requierment and Microcontroler system

Main Bios is a firmware to run Southbridge most main function are running LPC Bus interface.
with the programming commands that are already regulated by inter-IO interface available with programming sircuit The difference arrangement will cause the system to malfunction.The storage capacity of the ROM is also much larger so that programming is more detailed and complex to do.
Almost the entire System swiching on Laptop motherboard governed by this system,
Microcontroller can receive input ADP + as a command VALW standby on Line Power major in sircuit, the input signal is set based command programming so that if the signal input (adapter current detector) recorded in accordance with a range of programming, the EC will allow ADP + entry into sircuit and when the input detects (over voltage protection)and shoot down the entire system.
Embedded systems are also set based on the input signal when to instruct perform laptop battery charging system, this signal is usually referred to BAT_IN and active when the battery is installed, this detection will give the order to make the filling by sending a signal CHG_Enable Charger IC.Embedded systems are so much involved in laptop motherboard, they set up almost the entire input-output communication interface in circuit.
Beginning with a switching system in which the EC receives signals EC_ON from switch button, Embedded activated Southbridge by giving switching signal and turn signal VS (State enabled) then sends a signal to activate the gate driver power state based on pre-defined sequence.To get more understand look at the sample power


FIRST RESET SIGNAL


After All Power Supply for Always section presented and switches on circuit will begin to start VS Power state to boot up the system ,here it is to check reset signal requirement to have normal operation on circuit.
RSMRST#
When the Power, Bios ,Ec are OK, the RSMRST# will go Hi. In the other word,this pin go Low only when the systemreset .If BIOS data is error, RSMRST# won’t go HI.
When SIO(EC) get +V_RTC
thecrystal will work.


1. RTC have to be oscillating(32.768KHz).
2. RTCRST# have to be high.
3. RSMRST# have to be inactive (high).
4. PWRBTN# have a trigger.
5. LOW_BAT# have to be inactive (high).


If true, then EC will recieve SLP_S3# / SLP_S5 from ICH/PCH, in the old ICH or some deferent circuirity SLP_S3 and SLP_S5 will generate directly from ICH,or both EC and PCH having this signal also.
When All+V?S/+V powers are ready, PWR_GOOD will tie to high to turn on CPU powers(+VCCP and +VCC_CORE).






SB/PCH Power good--->SB/PCH pwr_btn--->PCH RUN
SUSB## from PCH to SIO pull up the signal SLP_S3# The signal is usedto shut power off /on through logic gate transistor or IC




SUSC# from PCH to SIO pull up the signal SLP_S5# The signal is usedto shut power off /on through logic gate transistor or IC


ICH/SB,MCH & CPU
IMVP_PWRGD => CLK_ENABLE# => RESET_OUT#=> ICH_PWRGD => PLTRST# => PCI_RST=> H_PWRGOOD


CPU generate the first cycle to read the BIOS code
CPU bus DMI LPC SPI
CPU ===> GMCH===> ICH===>SIO ===> BIOS



CPU MASTER POWER


VR_ON Enable--->+VCCORE 08VS to 1,5VS
Memory +VTT and +V1.5VS (DDR3) is ok, the PGOOD VTT_PWRGD pull high to CPU
First nd ICH will tie H_PWRGD to high ,then NB will tieCPURST# to reset CPU.




Crystal clock Oscillator CLOCK SUMMARY
(1) 32.768KHz to SIO Required +V_RTC and to ICH(chipset) also Required +V_RTC
(2) 49.152MHz to (audio controller) Required +V3S
(3) 27MHz : to Graphic chip (video controller)Required +V3S
(4) 14.318MHz : X1 to (clock Generator) Required +V3S


Make sure crystal is oscillating for EC(SIO),SB/ICH/PCH and VGA or it will no post


Clock Generator
Elementary required
1) Power : +V3S
(2) Crystal : 14.318MHz
(3) Control : PCISTOP# , CPUSTOP#_ is HI
When +VCC_CORE is ready, CLKEN#will go high to enable clock-Generator and turn all clock.
PCI_STOP# and CPU_STOP# must beat high otherwise some clocks will be turned off.






Clock out -->SIO(EC)-->PCH/SB-->NB-->CPU


LPC_Frame-->SB output signal is high


Note High signal can be identified by measuring 3.3V available






Voltage Swithes (VS)

VS is the voltage that appears after swicht on.This section activate after S5_ON ,EC and bios chip powered well and surely both firmware working.
This is General power system needs to running for all VS power rail